1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, particularly relates to a method for manufacturing a semiconductor device and a manufacturing apparatus respectively suitable for forming reliable wiring on a semiconductor substrate using technique for polishing and grinding in a damascene wiring forming process.
2. Description of the Related Art
Recently, processing technique for planarization for shallow trench isolation (STI), forming a tungsten (W) plug for transmitting a signal from each transistor to an interconnection layer and forming the interconnection layer has been important for manufacturing a semiconductor integrated circuit.
For the processing technique for planarization, polishing processing technique called chemical mechanical polishing (CMP) is representative.
Particularly, lately copper is used for wiring material. For planarization, a damascene process is mainstream and for example, is disclosed in Japanese Laid-Open No. 02-278822 and Japanese Laid-Open No. 08-83780.
In case copper is used for wiring material, there is a merit that the durability is enhanced and the resistance is reduced, compared with conventional type aluminum wiring, however, in the meantime, the failure of insulation due to a conductive ion by the diffusion of a copper ion into an oxide film is required to be considered.
In the damascene process, as shown in FIG. 9A, a barrier film 10 is formed as an interface between an oxide film 9 and copper 1 which is wiring material so as to prevent a copper ion from being diffused. In the damascene process, owing to the barrier film 10, the copper 1 is buried in a trench in a process from a step shown in FIG. 9A to a step shown in FIG. 9C.
For planarization by CMP, such processing that a dent (dishing) by overpolishing of a work piece and the whole dent (erosion) of a wiring assembled part are inhibited to obtain flat surface is required. Therefore, the elasticity of a polishing pad which is a processing tool is recently becoming harder.
Besides, as disclosed on pages 58 to 65 in proceedings of 2000 Chemical Mechanical Planarization for ULSI Multilevel Interconnection Conference, processing for planarization using fixed abrasive for high planarity and the inhibition of the use of abrasive is also executed.
Besides, the reduction of the resistance of wiring is enabled by the change of wiring material to copper, however, actual signal transmission speed is influenced by the dielectric constant of dielectric material (a dielectric interlayer) for isolating minute wiring. The narrow an interval between wiring is, the more remarkable the effect is and cannot be ignored.
In a device according to a rule of 0.18 μm, wiring is formed using the current silicon oxide film (dielectric constant: 4.1) as a dielectric interlayer, however, in a device according to a rule of 0.15 to 0.13 μm which will be massively produced, dielectric material (generally called low-k material) having a low dielectric constant of approximately 3.0 to 2.6 is required and in a device according to a rule of 0.1 μm or less, dielectric material having a lower dielectric constant of 2.5 or less is required.
For dielectric material having the dielectric constant of approximately 2.6, some candidates mainly of organic material can be given. However, there is a problem that the lower a dielectric constant is, the lower the mechanical strength of a film is. In a planarization process by CMP, the delamination and a crack of the film are easily caused and yield ratio is greatly deteriorated.
Particularly, the low-k material having the lower dielectric constant of 2.5 or less required for the rule of 0.1 μm or less is limited to brittle material such as porous silica, and it becomes a great problem in planarization.
Processing for planarization by CMP is executed by pressing a processed face on a pad and relatively rubbing the pad and a wafer, pouring polishing liquid including abrasive in a solvent. Therefore, machining frictional force which the processed face of the wafer receives during processing acts in the plane of the wafer to be a cause of the delamination or the breakage of a thin film on the surface. To avoid such a situation, low-k material that enables small-load polishing and has large mechanical strength is searched.